1. Field of the Invention
Embodiments of the invention relate to memory devices, and more particularly, in one or more embodiments, to data routing in memory devices.
2. Description of the Related Art
Memory devices typically include one or more memory arrays and ports for allowing an external device to access the memory arrays. Various routing schemes have been developed to provide transfer data between memory arrays and ports within a memory device.
FIGS. 1A and 1B (hereinafter, collectively referred to as FIG. 1) are a schematic plan view of a memory device employing a conventional routing scheme. The illustrated memory device 100 is a dynamic random access memory (DRAM). The illustrated portion of the memory device 100 includes first to fourth memory arrays 110a-110d, first to fourth master data line (MDL) pairs 120a-120d, and first to fourth port pads 150a-150d. A port pad and a circuit connected to the port pad for data input and output form a port. The illustrated portion can be repeated in the memory device 100, depending on the design of the memory device 100.
Each of the memory arrays 110a-110d has a first bank 111a-111d, a second bank 112a-112d, a third bank 113a-113d, a fourth bank 114a-114d, a first midgap 115a-115d, a second midgap 116a-116d, and local data line (LDL) pairs 130a-130d. The four banks 111a-114a, 111b-114b, 111b-114b, 111b-114b in each memory array 110a-110d extend parallel to one another in a row direction, as drawn in FIG. 1. A column direction is substantially perpendicular to the row direction, as drawn in FIG. 1. Each of the banks includes memory cells (for example, 8,192×256 or 16,384×512 cells) in a matrix form.
In the illustrated memory device 100, the first midgap 115a-115d of each memory array 110a-110d is positioned between the first bank 111a-111d and the second bank 112a-112d. The second midgap 116a-116d of each memory array 110a-110d is positioned between the third bank 113a-113d and the fourth bank 114a-114d. The first and second midgaps 115a-115d, 116a-116d run parallel to the four banks 111a-114a, 111b-114b, 111b-114b, 111b-114b in the row direction.
Each of the midgaps 115a-115d, 116a-116d includes a local midgap data line pair 117a-117d and a plurality of midgap switches 118a-118d. Each of the local midgap data line pairs 117a-117d includes two conductive lines extending in the row direction. The midgap switches 118a-118d serve to selectively make electrical connection between the local midgap data line pairs 117a-117d and the local data line pairs 130a-130d. The midgap switches 118a-118d are aligned with one another in the row direction within the same midgap. The midgap switches 118a-118d are also aligned in the column direction with the midgap switches in another midgap. For example, the midgap switches 118a in the first midgap 115a-115d are aligned in the column direction with the midgap switches 118a in the second midgap 116a-116d. The local midgap data line pairs 117a-117d and the local data line pairs 130a-130d together form data paths from the master data lines 120a-120d to memory cells in the banks, or vice versa during a read or write operation.
The local data line pairs 130a-130d serve to transfer data between the banks of one of the memory arrays 110a-110d and a respective one of the master data lines 120a-120d. The local data line pairs 130a-130d extend across the four banks and the midgaps in the column direction in one of the memory arrays 110a-110d. In the illustrated device 100, each of the local data line pairs 130a-130d includes two conductive lines. The local data line pairs 130a-130d are electrically coupled to the midgap switches 118a-118d aligned in the column direction within a memory array 110a-110d. 
Each of the first to fourth port pads 150a-150d includes a group of contacts 154a-154d. The group of contacts in a port pad can form a row or line. The contact can include a pad or input/output pad. In FIG. 1, each port pad 150a-150d is shown to include only one contact 154a-154d for simplicity, but each port pad 150a-150d includes more contacts depending on the design of the memory device. In the example shown, the contacts 154a-154d serve to provide electrical connection between the master data lines 120a-120d and an external device (not shown). Each of the contacts 154a-154d is formed of a conductive material. The number of the contacts 154a-154d per port pad may be selected based at least partially on the data input/output scheme that the memory device 100 employs. The contacts 154a-154d together provide data signals (e.g., representing bits) to the external device, or receive data signals from the external device.
The master data line pairs 120a-120d serve to transfer data between the local data line pairs 130a-130d and a respective one of the contacts 154a-154d. Each of the master data line pairs 120a-120d includes two conductive lines positioned between one of the port pads 150a-150d and a respective one of the memory arrays 110a-110d, extending in the row direction. The two conductive lines of a master data line pair run substantially parallel to each other and are electrically separated from each other. The master data line pairs 120a-120d are electrically separated from one another. Although FIG. 1 depicts the memory device 100 as including one pair of master data lines between a port pad and a memory array, the memory device 100 can include additional pairs of master data lines between the port pad and the memory array. Each of the additional pairs of master data lines is electrically connectable to a respective one of the contacts of the port pad via a pad switch.
The memory device 100 also includes a plurality of local data line switches 132a-132d. The local data line switches 132a-132d are positioned between one of the master data line pairs 120a-120d and an adjacent one of the memory arrays 110a-110d, and are aligned in the row direction. Each of the local data line switches 132 selectively provides electrical connection between one of the local data line pairs 130a-130d and the adjacent one of the master data lines 120a-120d. 
The memory device 100 also includes a plurality of pad switches 152a-152d. Each of the pad switches 152a-152d selectively provides electrical connection between one of the master data line pairs 120a-120d and a respective one of the contacts 154a-154d. Each of the contacts 154a-154d is electrically coupled to a respective one of the pad switches 152a-152d. Each of the master data line pairs 120a-120d may be electrically coupled to one or more of pad switches adjacent to a respective port pad.
Although not illustrated, the memory device 100 may further include other components, for example, an address register, a column decoding circuit, a row decoding circuit, a data input/output circuit, a bank control logic circuit, and sense amplifiers.
During operation, the switches 118a-118d, 132a-132d, 152a-152d are selectively turned on to transfer data to or from memory cells at selected addresses of the memory arrays 110a-110d. In the conventional arrangement, because each memory array is electrically connectable to the contacts of only one of the port pads, data stored in a memory cell of a memory array cannot be output via the contacts of another port pad. In addition, data provided to the contacts of one of the port pads can be stored only in a memory array that is electrically connectable to the contacts of the port pad, but not any other memory arrays.